The invention relates to a multi-bank memory chip that can operate with a controller designed for controlling a chip having a lesser number of banks and a method of operating such a chip.
Use of Dynamic Random Access Memory (DRAM) chips is well known in the computer field. Each memory chip contains at least one bank of a plurality of memory cells arranged in a row and column array. Each cell can contain a number of data bits. As memory technology has advanced, the capacity of chips has increased. For example, present day Synchronous DRAM (SDRAM) memory chips have a plurality of internal banks of the memory cells, for example, four or eight, with each bank having the row and column array of the memory cells. An individual cell of a memory bank of a multi-bank chip is addressed for purposes of reading or writing data by first selecting the memory bank and then addressing the row and column of the cell in the selected bank. The addressing is accomplished by a memory controller external of the chip that is often located on a computer system board, such as the mother board of a personal computer.
SDRAM chip internal banks of memory are separate entities. This allows the memory controller to operate multiple read/write requests at the same time with each request addressing a selected bank. When addressing a memory cell of a particular memory bank of the chip, the memory controller must produce bank identification, xe2x80x9cbank IDxe2x80x9d, bits with each memory command/address so that the chip will know the memory bank for which the address and commands are intended.
An SDRAM chip has an on-chip mode register which is programmed by the external controller with the bank selection (bank ID) bits and the cell address and commands. The set of address/command bits supplied to the chip mode register is often referred to as a xe2x80x9cMode Register Setxe2x80x9d (MRS). The details of the MRS bits, such as read and write commands, burst length and burst type used to execute various functions for different types of chips, such as DRAMs, is well known in the art and only the chip functions needed to describe the invention are presented here.
As an example to aid in the explanation of the invention, consider a chip of 1 Gb capacity that has four memory banks. To read data from a memory cell of one bank of the chip, two commands are needed. The format of the command and address of the chip MRS is represented as follows:
The legends used in the Chart above, which are relatively conventional, are explained below together with other explanatory material relative to the particular chip being considered.
CKExe2x80x94activates the system CLK (clock) signal when high (H) and deactivates the CLK signal when low (L). This can be used to initiate either a Power Down mode, Suspend mode or Self Refresh mode.
CSxe2x80x94enables the command decoder when low (L) and disables the command decoder when high (H). When the command decoder is disabled, new commands are ignored but previous operations continue.
A0-A15xe2x80x94the bits of the address bus. SDRAM breaks down the memory array address into ROW and Column addresses, and these addresses are sent by multiplex ROW and Column address at different times on the address bus. For example, a 512 Mb chip will have bits A0-A13 for ROW address bits and A0-A9, A11 for Column address bits.
RASxe2x80x94row address select. During a Bank Active command cycle, Address bits A0-A12 define the row address (RA0-RA12) when sampled at the rising clock edge.
CASxe2x80x94column address select. Bits A0-A9 and A11-A15. The number of bits of the Column address depends upon the number of memory cells activated by the Row address bits. As conventional, as the capacity of DRAM chips becomes larger, the size of each row stays relatively constant due to memory power consideration. Therefore, the column address usually has fewer bits than a ROW address.
WExe2x80x94write enable. When active, indicates the write operation to the Column memory cell addressed.
BAxe2x80x94bank address field. A four bank DRAM chip MRS has two bank ID bits BA0, BA1 to select to which of the four banks a command applies. An eight bank chip would have three bank ID bits BA0, BA1, BA2.
A10(=AP)xe2x80x94is used to invoke the autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and the bank ID bits BA0, BA1 define the bank to be precharged. If A10 is low, autoprecharge is disabled. During a precharge command cycle, A10 (=AP) is used in conjunction with the bank ID bits BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge.
FIG. 1 shows part of a typical four bank chip 10, such as found in a DDR2 512 Mb chip. Only the parts of the chip address logic and circuits pertinent to the invention are shown. The read and write functions are standard and are omitted. The chip 10 is operated by an external controller 60. Chip 10 has four memory banks, 12-0, 12-1, 12-2 and 12-3, each bank having a plurality of memory cells arranged in rows and columns. The cell of a memory bank 12 is addressed by instructions supplied by an external controller 60. That is, the controller 60 is not part of the chip and is typically located in another part of the computer in which the chip 10 is being used. Each memory bank 12 has corresponding sense amplifiers 13 and outputs to an input/output (I/O) gating mask logic circuit 15. All of this is conventional.
The controller 60 produces instructions for only two bank ID bits, BA0 and BA1. Thus, it is designed to operate with a chip in which there are no more than four memory banks 12. Signals, such as those referred to in Chart A above, are applied as instructions from the external controller 60 to a chip control logic circuit 20 that includes a command decoder 22 that decodes the instructions from the controller 60. There is also an address register 30 to which the address bits A0-A12 and the two bank ID bits BA0 and BA1 are input and stored.
The bank select ID bits BA0 and BA1 from the address register 30 are applied to a bank control logic circuit 34 to determine which of the four banks 12-0, 12-1, 12-2 and 12-3 is to be selected for a read or write operation. Depending upon which one of the four banks that is selected, a corresponding bank row decoder 40-1, 40-1, 40-2 and 40-3, as well as a corresponding bank column decoder 42-0, 42-1, 42-2 and 42-3 also is selected. To address a memory cell of the selected bank 12-0 to 12-3, the RAS (row address select) address bits A0-A12 are appropriately applied to a row address multiplexer 44. Next, the CAS (column address select) bits A0-A9, A11 and A12 are applied to a column address counter and latch circuit 46. There is also a refresh circuit 48 that recharges the chip memory cell transistors (at AP=A10). Read and write operations are performed on the selected cell of a bank by selecting one of the four banks 12-0 to 12-3 by using the two bank ID bits BA0, BA1 and the column and row addresses.
Charts B1 and B2 show certain of the details of two different size chips. Chart B1 illustrates a four bank 512 Mb chip with the bank ID bits BA0 and BA1. The autoprecharge occurs at A10, with the row address RAS being from A0-A13 and the column address CAS being at A0-A9, A11. Chart B2 illustrates a four bank chip of 1 Gb capacity. Therefore, it has one additional bit A0-A14 for the row address.
As the number of memory banks of a chip increases the external memory controller must accommodate this. This means that extra logic and IO (input/output) support must be provided for the bank Id BA field. For example, if the chip has more than four banks of memory, the size of the bank ID field must increase. As should be obvious, if the memory controller outputs instructions for two bank ID bits for bank selection, it can select any one of four banks on a chip. If the memory controller outputs instructions for three bank ID bits, it can select one of up to eight banks on a chip. The latter is shown on Chart B2-1.
A problem arises when chips with a large number of banks, for example eight, are to be used with memory controllers that were designed to operate with chips having a fewer number of banks, for example, four. Such a controller would only be capable of producing two bank ID bits BA0 and BA1. Therefore, it would be desirable to provide a solution to a problem of xe2x80x9cbackward compatibilityxe2x80x9d so that an existing controller, such as one designed to operate with chips having four memory banks, can operate a chip with a higher number of banks, such as eight banks. Accordingly, a need exists to be able to operate a chip having a given number of memory banks by a controller designed to operate a chip with a fewer number of banks.
The invention provides for configuring and operating a chip with a number of banks of memory to be backward compatible with controllers designed to operate chips having a lesser number of banks. The invention accomplishes this by providing an optional control (bit) on the chip Mode Register Set (MRS). The use of this control activates corresponding logic in the chip to move one of the bits used to address a memory cell, such as one of the row address bits, to a position of the bank ID field. This provides a greater number of bank ID bits to select memory banks of a chip. Therefore, in accordance with the invention, a high number bank chip can accept a command supplied by a controller designed to operate a chip with a fewer number of banks and has a format of a fewer bank ID bits.
In accordance with the invention, for example, consider an SDRAM chip with eight banks that is operated by a controller designed to operate chips having four banks. One bit of the chip MRS is used as a control to designate the chip as being either in the lower number, e.g., four bank mode, or the higher number, e.g., eight bank mode. When the chip is operated in the higher bank number mode by an external controller designed for this, such as a controller producing instructions for three bank ID bits which can select one of eight banks, all three bits of the bank address register and all row or column addresses are operated in the normal manner. In the lower bank number mode, only two bank ID bits come from the external control, which is a memory controller which only supports four bank operations. In this case, the chip will use one of the address as the third bank ID bit and apply the complete three bit bank ID for both the RAS and corresponding CAS operations to select one of the eight banks. In a preferred embodiment of the invention, any row address bit can be used as this third bank ID bit.
This invention is described with reference to an SDRAM type chip but is applicable with various memory chips, such as SDRAM, DDR1 SDRAM and DDR2 SDRAM, as well as any further DRAM architecture with multiple internal banks structure where the bank numbers are different.